1. Field of the Invention
The present invention relates to a resistor-capacitor (RC) delay circuit, and more particularly to a RC delay time stabilizing circuit.
2. Description of the Conventional Art
Generally, a semiconductor memory device controls delay time by using a RC delay circuit which consists of a resistor and a capacitor in order to maintain the time margin of signals. Here, the RC delay circuit charges/discharges an inputted signal to the capacitor through the resistor for thereby delaying the signal.
FIG. 1 illustrates a conventional RC delay circuit.
As shown therein, the conventional RC delay circuit includes an inverter IN1 which inverts an input signal IN, a RC delay unit 10 which delays an output from the inverter IN1 and a NOR gate NR1 which NORs outputs from the inverter IN1 and the RC delay unit 10, the RC delay unit 10 consisting of a resistor R and an n-type MOS capacitor 12.
FIG. 2 shows a signal wave form when an input signal IN having a single cycle is applied. Referring to FIG. 2, in such conventional RC delay circuit, when the input signal IN is inputted through the inverter IN1 and the resistor R to the MOS capacitor 12, the MOS capacitor 12 of the RC delay unit 10 repeatedly performs charging and discharging in accordance with a level of the input signal IN. However, due to the characteristic of the NOR gate NR1, when the input signal IN is transited to a high level from a low level, a delay time d1 of an output signal OUT is determined by an output signal B from the RC delay unit 10, while the delay time d1 thereof is determined by an output signal A from the inverter IN1 when the input signal IN is transited from the high level to the low level. Accordingly, the output signal OUT from the NOR gate NR1 has the delay time by d1 to respect to the input signal IN. FIG. 3 illustrates a signal wave form when a periodic input signal IN is applied. As mentioned above, the conventional RC delay circuit generates the output signal OUT having a predetermined delay time to each cycle of the periodic input signal IN. Ideally, the output signal OUT has the same delay time in each cycle. However, when the periodic input signal IN is charged to the MOS capacitor 12 through the inverter IN1 and the resistor R, a second cycle of the input signal IN may be inputted to the MOS capacitor 12 when a first cycle of the input signal IN is not fully charged in the capacitor 12. In that case, the level of the output signal B of the RC delay unit 10 decreases and accordingly the delay time d2 of the output signal OUT is reduced. Thus, the delay time d2 of the second cycle becomes shorter than the delay time d1 of the first cycle.
As described above, the conventional RC delay circuit has a problem that the periodic input signal IN is applied, the RC delay time of each cycle may not be identical. Accordingly, the semiconductor memory device can not maintain the time margin of the signals due to the unstable RC delay operation.